Design of a 0. 8-5. 2 GHz CMOS Wideband LNA Employing Multiple Feedback Loop Technique

WAN Qiuzhen, WU Xiaoting, XU Meng, XU Dandan

Abstract

Based on the traditional common-gate (CG) amplifier configuration, a 0. 8 — 5. 2 GHz wideband LNA employing multiple feedback loop technique using a 0. 18 ^m CMOS technology was presented. The negative feedback structure of the LNA can improve the noise figure and input impedance matching, while it does not require additional power consumption. The dual positive feedback structure of the LNA can also increase the flexibility of input MOS transistor transconductance, and in turn control the input impedance matching by the output load impedance. The combination of these techniques would optimize the power gain, input impedance, and noise figure simultaneously over a wide frequency range. Post-layout simulation results show that the wideband LNA has a power gain of 12. 0 — 14. 5 dB. an input return loss S11 of —8. 0—— 17. 6 (IB, an output return loss S-,2 of  10. 0- 32. 4 dB, and a reverse isolation S,2 of less — 45. 6 dB in the frequency range of 0. 8~5. 2 GHz. A noise figure of 3. 7 — 4. 1 dB was also obtained in the required band with a power dissipation of 9. 0 mW under a supply voltage of 1.5 V. The input third-order intercept point (IIP3) is — 4. 0 dBm at 3 GHz. The chip area including testing pads is only 0. 7 mmX 0. 8 mm.

 

 

Keywords:  CMOS :  RF integrated circuits,  low noise amplifier (LNA),  wideband,  multiple feedback loop technique


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